A Compiled-code Simulator with Reduced Edge Evaluation

Two major approaches for the digital design simulation can be classified into event-driven and levelized-code method. The drawback of event-driven simulation is low efficiency while the levelized-code simulation has problems in supporting asynchronous design. Since most digital designs are synchronous digital we implemented a levelizedcode simulator targeting synchronous digital design. Levelization is used to determine the sequence of the evaluation when clock stays high or low. We used the levelization method to the evaluation at the clock edge. The new evaluation method is proven valuable fro enhancing the simulation speed up to 30% in real design examples. The overall simulator speed is up to 7 times faster than VCS and 80 times faster than Verilog-XL.